Boolean Logic Truth Table Generator
Enter a boolean expression to generate its truth table. Variables A-F are auto-detected.
Last reviewed: April 2026New to this tool? Click here for instructions
How to use the Boolean Truth Table Generator
To use the Boolean Logic Truth Table Generator, simply enter a boolean expression using variables A-F and operators. Click 'Generate Table' to create the truth table for all combinations of your variables. Variables are single letters A through F (case-insensitive). Parentheses are fully supported for grouping sub-expressions.
When to use the Boolean Truth Table Generator in real workflows
The Boolean Logic Truth Table Generator is useful for debugging complex conditionals, verifying that your logic handles all edge cases, and simplifying redundant conditions. This tool is beneficial in various fields including digital circuits, programming, and search queries.
How it works
The evaluator accepts both word-form and symbol-form operators: AND, OR, NOT, XOR, NAND, NOR, IMPLIES. Variables are auto-detected and can be used in expressions. For expressions with 5 or more variables, the Quine-McCluskey algorithm or Espresso replaces K-maps.
Tips, edge cases, or limitations
The truth table output can be exported as CSV and fed into external minimization software for larger expressions. For expressions with 5 or more variables, the Quine-McCluskey algorithm or Espresso replaces K-maps. The truth table output can be exported as CSV.
Frequently Asked Questions
Enter any boolean expression and instantly generate a full truth table, Karnaugh map, and simplified sum-of-products form — entirely in your browser.
What This Tool Does
This tool accepts boolean expressions with 2–8 variables and produces a complete truth table — one row per input combination, with intermediate column values for each sub-expression. For expressions with 2, 3, or 4 variables, a Karnaugh map renders automatically with minterm groupings highlighted in distinct colors. The tool then applies the Quine–McCluskey algorithm to output a minimized Sum-of-Products (SOP) form, reducing your expression to its simplest equivalent gate network.
Supported operators cover the full set used in digital logic and formal reasoning: AND, OR, NOT, XOR, NAND, NOR, and IMPLIES (written -> or →). Every computation runs client-side — no expression you enter is uploaded, stored, or logged anywhere outside your local browser session. 🔒
How to Use It: Step-by-Step with Worked Example
The fastest way to learn the interface is to work through a concrete expression. The example below uses three variables and exercises the K-map grouping and SOP output in a way you can verify by hand.
Entering Your Expression
Type your expression into the input field at the top of the tool. The parser accepts operator keywords or their symbolic equivalents: AND / && / ·, OR / || / +, NOT / ! / ~, XOR / ^, NAND, NOR, and IMPLIES / ->. Variable names must be single uppercase letters (A–H). Hit Generate or click Try Example to pre-load (A AND B) OR (NOT C).
Reading the Truth Table Output
Each row in the output table corresponds to one binary input combination, enumerated in standard binary order from 000 to 111. Intermediate columns show the value of each parenthesized sub-expression, making it straightforward to trace how the final output was computed for any row. Rows where the output is 1 are the minterms — the numbered input combinations that your expression covers.
Interpreting the K-map
Switch to the K-map tab after generating a truth table with 4 or fewer variables. Cells are arranged in Gray code order on both axes — not binary order — so that visually adjacent cells are also logically adjacent. Grouped minterms appear highlighted in distinct colors; each color corresponds to one product term in the simplified SOP.
Copying and Downloading Results
The Copy button copies the truth table as tab-separated values (TSV) suitable for pasting directly into Excel or Google Sheets. Download as CSV saves a file with column headers included. The simplified SOP expression can be copied from the output panel separately.
Worked Example: (A AND B) OR (NOT C)
- Expression
(A AND B) OR (NOT C)- Variables
- A, B, C — 3 variables; standard binary row ordering in the table, Gray code ordering in the K-map
- Enter the expression. Type
(A AND B) OR (NOT C)into the expression field and press Generate, or click Try Example to pre-load it automatically. - Read the 8-row truth table. Rows run from A=0,B=0,C=0 through A=1,B=1,C=1. The output column shows
1for rows 000, 010, 100, 110, and 111 — these are minterms 0, 2, 4, 6, and 7. Rows 001, 011, and 101 (minterms 1, 3, 5) output0. - Switch to the K-map tab. Cells are arranged in Gray code order on both axes. Minterms 0, 2, 4, and 6 form a group of four — spanning all combinations where C=0 — so A and B cancel, leaving the term C̄.
- Identify the second group. Minterm 7 (A=1, B=1, C=1) is not covered by the group of four. It pairs with minterm 6 (A=1, B=1, C=0) — both share A=1 and B=1, so C cancels, yielding the term AB. Two prime implicant groups total: {0,2,4,6} → C̄ and {6,7} → AB.
- Read the simplified SOP. The output panel displays
AB + C̄. When C is 0 the expression is always 1 (C̄ covers minterms 0, 2, 4, 6), and when both A and B are 1 it is also 1 (AB covers minterms 6 and 7), with minterm 6 covered by both groups. - Export results. Click Copy to grab the table as TSV, or Download as CSV to save it. The simplified SOP string
AB + C̄can be copied from the SOP output panel independently.
Expected output: 8-row truth table with minterms 0, 2, 4, 6, 7 outputting 1; K-map with two highlighted groups ({0,2,4,6} in blue, {6,7} in orange); simplified SOP: AB + C̄.
| Row # | A | B | C | NOT C | A AND B | Output |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 |
| 2 | 0 | 1 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 0 | 0 | 0 |
| 4 | 1 | 0 | 0 | 1 | 0 | 1 |
| 5 | 1 | 0 | 1 | 0 | 0 | 0 |
| 6 | 1 | 1 | 0 | 1 | 1 | 1 |
| 7 | 1 | 1 | 1 | 0 | 1 | 1 |
Truth Table Basics: Rows, Columns, and Gray Code Ordering
How Row Count Is Determined
With n input variables, a truth table contains exactly 2n rows — one for every possible binary assignment of those variables. Three variables yield 8 rows; four variables yield 16; eight variables yield 256. NIST defines Boolean algebra as a two-valued algebraic system where each variable takes exactly one of two values (0 or 1) at any point in time, which is why this row-count formula holds without exception.
Standard Binary vs. Gray Code Ordering
The tool defaults to standard binary order in the truth table display: 000, 001, 010, 011, 100, 101, 110, 111. This maps cleanly to decimal row indices 0 through 7 and makes minterm numbering unambiguous. Gray code order runs differently: 000, 001, 011, 010, 110, 111, 101, 100. Each successive value in a Gray code sequence differs from its predecessor by exactly one bit — a property called unit distance.
Why Gray Code Matters for K-map Adjacency
Karnaugh maps arrange their row and column headers in Gray code order specifically to enforce logical adjacency between neighboring cells. Plain binary ordering would let visually adjacent cells differ in two or more variables, making drawn groupings useless for variable cancellation. Gray code ordering transforms the 2D grid into a valid topological representation of the Boolean hypercube, where every pair of neighboring cells — including wrap-around edges — differs by exactly one variable assignment.
Karnaugh Maps Explained: Grouping for Simplification
Reading a K-map Cell
Each cell in a Karnaugh map corresponds to one minterm. The cell's position is determined by the Gray code values of the row and column headers — for a 3-variable map, one variable labels two rows while the other two variables label four columns in Gray order (00, 01, 11, 10). A cell containing 1 is a minterm; a cell containing 0 is a maxterm; a cell containing X is a don't-care condition.
Forming Groups of 1, 2, 4, and 8
Valid groupings must be rectangular (or wrap-around rectangular), must contain only 1s and Xs, and must have a size that is a power of 2 — groups of 1, 2, 4, 8, or 16 cells. Larger groups are always preferable: each doubling of group size eliminates one variable from the resulting product term. Groups may wrap around map edges (toroidal adjacency) — the leftmost column is logically adjacent to the rightmost, and the top row is adjacent to the bottom. Don't-care conditions can be included to enlarge a group, achieving better minimization even though their output value is irrelevant.
Extracting the Simplified Expression
For the worked example (A AND B) OR (NOT C), the group {0,2,4,6} covers all four cells where C=0, regardless of A and B. Since A and B each take both values within the group, they cancel, leaving only C̄. The pair {6,7} covers cells where A=1 and B=1 regardless of C; C cancels, leaving AB. The final SOP is the OR of those two terms: AB + C̄.
Quine–McCluskey as the Algorithmic Equivalent
Visual K-map grouping becomes impractical beyond four variables because a flat 2D grid cannot preserve adjacency intuition at that scale. The Quine–McCluskey tabulation method — introduced by W.V. Quine in 1952 and extended by E.J. McCluskey in 1956 — performs the same simplification algorithmically. It groups minterms by popcount (number of 1-bits in their binary representation), then iteratively merges pairs that differ by exactly one bit, replacing the differing bit with a dash. When no further merging is possible, the remaining patterns are prime implicants. The tool uses this algorithm for all expression sizes and then applies Petrick's method to select an essential cover when multiple minimal SOP forms exist.
Operator Reference: AND, OR, NOT, XOR, NAND, NOR, IMPLIES
The table below consolidates every operator the tool supports, including the IEEE 91 standard symbol for each logic gate, the plain-English output rule, and typical deployment contexts. Operator precedence follows standard Boolean algebra convention: NOT > AND > XOR > OR > IMPLIES. When in doubt, add parentheses — the parser respects them.
| Operator | Syntax (tool) | IEEE 91 Symbol | Output Rule | Digital Logic Use | Software / Code Use |
|---|---|---|---|---|---|
| AND | AND / && / · |
& | 1 only when all inputs are 1 | Enable/masking gates, address decoding | Guard clauses, short-circuit evaluation |
| OR | OR / || / + |
≥1 | 1 when at least one input is 1 | Interrupt aggregation, fan-in structures | Default/fallback conditions |
| NOT | NOT / ! / ~ |
1 (bubble) | Inverts the single input | Signal inversion, active-low logic | Negating boolean flags |
| XOR | XOR / ^ |
=1 | 1 when inputs differ | Parity generation, half-adder sum bit | Checksums, AES round-key mixing |
| NAND | NAND |
& (with bubble) | 0 only when all inputs are 1 (NOT-AND) | Universal gate — entire CPUs can be built from NAND alone; dominates CMOS fabrication | Rarely expressed directly; implicit in compiled code |
| NOR | NOR |
≥1 (with bubble) | 1 only when all inputs are 0 | Second universal gate; used in SRAM cells | Checking that no flags in a set are active |
| IMPLIES | IMPLIES / -> / → |
(no IEEE gate symbol) | 0 only when A=1 and B=0 | Formal verification, state-machine constraints | TLA+, Z notation, propositional proof systems |
Two operators deserve special attention. NAND is functionally complete — any Boolean function expressible with AND, OR, and NOT can be re-expressed using only NAND gates. This is why NAND dominates CMOS fabrication: a single gate type simplifies the physical design rule set. NOR carries the same functional-completeness property and is the second universal gate.
Common Use Cases: Circuit Design, Testing, and Boolean Algebra
Digital Logic Design and Gate Minimization
In combinational circuit design, a truth table is the starting specification. Once the desired input-output behavior is captured in tabular form, the designer derives an SOP or POS expression, then minimizes gate count before sending the design to synthesis. Reducing gate count directly lowers both power consumption and silicon area — as covered in Patterson & Hennessy's Computer Organization and Design, even a modest reduction in logic depth can cascade into meaningful power savings at chip scale. Running a 4-variable expression through the K-map minimizer here before opening your HDL editor can eliminate unnecessary logic before a single line of Verilog is written.
Software Conditional Logic Verification
QA engineers and developers use truth tables to exhaustively enumerate every combination of boolean inputs to a branching condition — something that's otherwise easy to miss in code review. For a condition like (isAdmin && isActive) || !isLocked, a 3-variable truth table reveals exactly which input states trigger each branch. Regex Tester serves a parallel purpose for string-matching logic: enumerate the pattern's behavior across boundary inputs rather than relying on intuition. De Morgan's theorems offer a systematic way to rewrite negated conjunctions: NOT(A AND B) = (NOT A) OR (NOT B) and NOT(A OR B) = (NOT A) AND (NOT B) — useful when refactoring deeply nested negations in code.
Boolean Algebra Coursework and Exam Prep
Students can enter a hand-derived SOP or POS expression and immediately verify whether it matches the original truth table specification. Because the tool shows intermediate sub-expression columns, it also functions as a step-by-step checker: if your hand computation diverges from the tool output at a specific column, that column identifies exactly where the error occurred. The JSON Schema Validator follows the same philosophy for data validation — surface errors at the specific constraint that failed, not just a pass/fail verdict.
Edge Cases and Limitations
A few constraints and parsing behaviors are worth knowing before you run into them mid-session.
K-map visualization is capped at 4 variables. For 5–8 variables, the tool displays the full truth table and the Quine–McCluskey SOP result, but no graphical K-map renders — K-maps beyond 16 cells are rarely useful for human-driven minimization anyway.
Variable names are case-sensitive. A and a are treated as distinct variables. Mixing cases in a single expression produces more variables than intended and expands the truth table accordingly.
Operator precedence applies even without parentheses. The expression A OR B AND C parses as A OR (B AND C) because AND binds more tightly than OR. If you intended (A OR B) AND C, the parentheses are required — the parser will not guess intent from context.
IMPLIES is right-associative. The expression A -> B -> C parses as A -> (B -> C), matching standard propositional logic convention. This differs from left-associative operators like AND and OR.
Tautologies and contradictions are flagged. If every row in the output column is 1, the status bar reads Tautology. If every row is 0, it reads Contradiction. Both are common in formal verification contexts and easy to accidentally introduce when chaining IMPLIES expressions.
Behind the Scenes: Parsing and Evaluation Algorithm
Tokenization and Recursive Descent Parsing
The expression string is first tokenized into a flat sequence of operators, variable names, and parentheses. A recursive descent parser then consumes that token stream, building an Abstract Syntax Tree (AST) where each internal node is an operator and each leaf node is a variable or boolean literal. The recursive structure handles arbitrary nesting depth without an explicit stack — the call stack provides the implicit recursion. Operator precedence is encoded directly into the grammar rules: the IMPLIES production calls the OR production, which calls the XOR production, which calls the AND production, which calls the NOT production, enforcing NOT > AND > XOR > OR > IMPLIES automatically.
Truth Value Enumeration
With the AST in hand, the evaluator iterates over all 2n input combinations using a simple integer counter from 0 to 2n−1. For each counter value, variable assignments are extracted via bitwise shifts: variable k gets the value of bit k of the counter. The AST is evaluated depth-first for that assignment, producing one output bit. All output bits are collected into the minterm list in a single O(2n) pass.
Quine–McCluskey Minimization Pass
Minterms are sorted by popcount (number of 1-bits). The algorithm merges adjacent groups — pairs that differ in exactly one bit position — replacing the differing bit with a dash to produce a new pattern. This merge process repeats iteratively until no new patterns can be formed; the remaining patterns are the prime implicants. When multiple prime implicant sets cover all minterms, Petrick's method selects the minimal cover. The overall time complexity is O(3n), which is why the practical ceiling sits near n = 20 variables before runtime becomes noticeable in a browser context. At 8 variables (256 rows), the computation completes in well under one millisecond on any modern device.
| Expression Size | Gates Before Minimization | Gates After Minimization | Reduction |
|---|---|---|---|
| 3-variable (8 minterms) | 11 | 4 | 64% |
| 4-variable (16 minterms) | 22 | 8 | 64% |
| 5-variable (32 minterms) | 47 | 14 | 70% |
| Operator | Digital Logic Use Case | Software / Code Use Case | Notes / Gotchas |
|---|---|---|---|
| AND | Masking bits; enabling a signal only when multiple conditions hold simultaneously | Guard clauses; compound if-conditions | Software AND short-circuits (skips right operand if left is false); hardware evaluates both inputs fully |
| OR | Interrupt aggregation; any-of-N trigger | Fallback/default conditions; feature flags | Software OR short-circuits; hardware evaluates both. Inclusive-OR vs. XOR confusion is common |
| NOT | Signal inversion; active-low enable lines | Negating a flag; inverting a predicate | Double negation (NOT NOT A = A) is a common simplification target |
| XOR | Parity generation; half-adder sum; toggle flip-flops | Difference detection; AES key mixing; swap without temp variable | XOR is its own inverse: A XOR A = 0; A XOR 0 = A |
| NAND | Universal gate; standard cell in CMOS; minimum-inversion logic | Rarely written explicitly; compiler emits NAND-equivalent patterns | Functional completeness means any logic network can be re-expressed in NAND-only |
| NOR | Universal gate; SRAM cell cross-coupled NOR latches | Checking that a set of flags is entirely inactive | Like NAND, NOR alone can implement any logic function — useful in NOR-flash architecture |
| IMPLIES | Constraint specification in formal verification tools | TLA+, Z notation, Alloy model specifications | A → B is false only when A is true and B is false; commonly misread as "if-then" in natural language, which implies exclusion |